RFR: 8328998: Encoding support for Intel APX extended general-purpose registers

[Steve Dohrmann]

On Mon, 15 Apr 2024 17:33:06 GMT, Vladimir Kozlov <kvn at openjdk.org> wrote:

>> Add instruction encoding support for Intel APX extended general-purpose registers:
>> 
>> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>> 
>> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 669:
> 
>> 667:       // [base + disp]
>> 668:       assert(((base_enc & 0x7) != 4), "illegal addressing mode");
>> 669:       if (disp == 0 && no_relocation &&  ((base_enc & 0x7) != 5)) {
> 
> We loost information with this change. Can it be done as `is_r13_encoding(base_enc)` and `is_r12_enxoding(base_enc)`?

Thanks for the comment.  The "& 0x7" style was suggested to me by @sviswa7 as a efficient way to check for r12, r20, r28 in the assert, and for r13, r21, r29 in the if statement.  I originally was comparing against each new APX register encoding.  The style in the PR is concise but it can be done either way.  What do you think?

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1567874941