RFR: 8321021: RISC-V: C2 VectorUCastB2X [v3]

[Fei Yang]

On Fri, 8 Mar 2024 12:17:15 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Hi,
>> Can you help to review the patch to add support for some vector intrinsics?
>> Also complement various tests on riscv.
>> Thanks.
>> 
>> ## Test
>> test/hotspot/jtreg/compiler/vectorapi/
>> test/hotspot/jtreg/compiler/vectorization/
>
> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fix typo

Hi, I have one comment after a brief look.

src/hotspot/cpu/riscv/riscv_v.ad line 3397:

> 3395:   predicate(Matcher::vector_element_basic_type(n) == T_FLOAT);
> 3396:   match(Set dst (VectorCastL2X src));
> 3397:   effect(TEMP_DEF dst);

I see you added `TEMP_DEF dst` for some existing instructs like this one here. Do we really need it?
I don't see such a need when reading the overlap constraints on vector operands from the RVV spec [1]:


A destination vector register group can overlap a source vector register group only if one of the following holds:

    The destination EEW equals the source EEW.

    The destination EEW is smaller than the source EEW and the overlap is in the lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi v0, v0, 3 is legal, but a destination of v1 is not).

    The destination EEW is greater than the source EEW, the source EMUL is at least 1, and the overlap is in the highest-numbered part of the destination register group (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).


[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vec-operands

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PR Review: https://git.openjdk.org/jdk/pull/18040#pullrequestreview-1926897564
PR Review Comment: https://git.openjdk.org/jdk/pull/18040#discussion_r1519134205