RFR: 8326385: [aarch64] C2: lightweight locking nodes kill the box register without specifying this effect

[Roman Kennke]

On Mon, 11 Mar 2024 09:26:48 GMT, Roberto Castañeda Lozano <rcastanedalo at openjdk.org> wrote:

> This changeset introduces a third `TEMP` register for the intermediate computations in the `cmpFastLockLightweight` and `cmpFastUnlockLightweight` aarch64 ADL instructions, instead of using the legacy `box` register. This prevents potential overwrites, and consequent erroneous uses, of `box`.
> 
> Introducing a new `TEMP` seems conceptually simpler (and not necessarily worse from a performance perspective) than pre-assigning `box` an arbitrary register and marking it as `USE_KILL`, an alternative also suggested in the [JBS issue description](https://bugs.openjdk.org/browse/JDK-8326385). Compared to mainline, the changeset does not lead to any statistically significant regression in a set of locking-intensive benchmarks from DaCapo, Renaissance, SPECjvm2008, and SPECjbb2015.
> 
> #### Testing
> 
>  - tier1-7 (linux-aarch64 and macosx-aarch64) with `-XX:LockingMode=2`.

I've got a question.
Also, what about the other arches?

src/hotspot/cpu/aarch64/aarch64.ad line 16022:

> 16020: %}
> 16021: 
> 16022: instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp, iRegPNoSp tmp2, iRegPNoSp tmp3)

Do we need to specify the box register at all, if we never use it? It means that the register allocator assigns an actual register to it, right? This could be a problem in workloads that are both locking-intensive *and* with high register pressure. You may just not see it with dacapo, etc, because aarch64 has so many registers to begin with.

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PR Review: https://git.openjdk.org/jdk/pull/18183#pullrequestreview-1927918533
PR Review Comment: https://git.openjdk.org/jdk/pull/18183#discussion_r1519772909