RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v22]

[Jatin Bhateja]

On Tue, 21 May 2024 17:18:04 GMT, Vladimir Kozlov <kvn at openjdk.org> wrote:

>> Is it enough to have AVX512F present for APX? What about Knight CPUs which have limited AVX512 features?
>
> You should add code which checks CPUID features bit to set `UseAPX`. Or set it to `false` unconditionally in this PR regardless UseAVX value with comment "APX is not supported on this CPU". Otherwise someone will switch it on command line on avx512 machine.
> 
> Or we should push [#18562](https://github.com/openjdk/jdk/pull/18562) first. Which I prefer.

> What about Knight CPUs which have limited AVX512 features?

Any VEX encoded instruction directly accessing an EGPR operand or a memory operand with EGPR BASE / INDEX must be promoted to Extended EVEX encoding. 

Please consider following example:-

CPROMPT>xed64 -64 -d 62 da 7d 28 18 13
62DA7D281813
ICLASS:     VBROADCASTSS
CATEGORY:   BROADCAST
EXTENSION:  AVX512EVEX
IFORM:      VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512
ISA_SET:    AVX512F_256
ATTRIBUTES: DISP8_TUPLE1 MASKOP_EVEX MEMORY_FAULT_SUPPRESSION 
SHORT:      vbroadcastss ymm2, dword ptr [r27]
  
Since broadcast accesses an EGPR register and a non-512 bit vector hence target CPU must also be capable of supporting vector length orthogonality which necessitate AVX512VL feature.

APX in true sense is a mix of both ISA extension (new PUSH/POP2, PPX and NDD instructions, JMPABS, COND COMPARE etc..) and also provisions additional general purpose registers to existing ISA, in the later case user may expect to benefit by saving costly 3 cycles spills from GPR to XMM enabled with UseFPUForSpilling.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1621948136