RFR: 8365732: RISC-V: implement AES CTR intrinsics [v3]

[Anjian Wen]

On Thu, 28 Aug 2025 02:29:57 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Anjian Wen has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   change some name and format
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2613:
> 
>> 2611:     uint64_t maskIndex = 0xaaul;
>> 2612:     __ mv(t0, maskIndex);
>> 2613:     __ vsetvli(x1, x0, Assembler::e8, Assembler::m1);
> 
> Please note that `x1` is a special register (return address) on riscv64. Why not use `t0` instead? I mean:
> 
>     __ vsetvli(t0, x0, Assembler::e8, Assembler::m1);
>     __ mv(t0, maskIndex);
>     __ vmv_v_x(v0, t0);

Thanks for the review! I think we can use t0 here to avoid x1, done!

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2644:
> 
>> 2642: 
>> 2643:     __ bind(L_encrypt_next);
>> 2644:     __ add(t1, saved_encrypted_ctr, used);
> 
> Can we avoid use `t1` here since we already have `vl` as its alias?
> We can declare a `tmp` register and let it alias `c_rarg7`. Like `const Register tmp = c_rarg7;`
> Then we can use this `tmp` here instead.

done

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2646:
> 
>> 2644:     __ add(t1, saved_encrypted_ctr, used);
>> 2645:     __ lb(t0, Address(t1));
>> 2646:     __ lb(t1, Address(in));
> 
> Should we use `lbu` instead of `lb` here?

yes，I think encrypt a single byte should be unsigned here，we better change it to lbu to avoid some corener error，done

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2306285456
PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2306285573
PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2306285782