RFR: 8359965: Enable paired pushp and popp instruction usage for APX enabled CPUs [v5]

[Jatin Bhateja]

On Thu, 17 Jul 2025 17:17:07 GMT, Srinivas Vamsi Parasa <sparasa at openjdk.org> wrote:

>> The goal of this PR is to enhance the existing x86 assembly stubs using PUSH and POP instructions with paired PUSHP/POPP instructions which are part of Intel APX technology.
>> 
>> In Intel APX, the PUSHP and POPP instructions are modern, compact replacements for the legacy PUSH and POP, designed to work seamlessly with the expanded set of 32 general-purpose registers (R0–R31). Unlike their predecessors, they use the new APX (REX2-based) encoding, enabling more uniform and efficient instruction formats. These instructions improve code density, simplify register access, and are optimized for performance on APX-enabled CPUs.
>> 
>> Pairing PUSHP and POPP in Intel APX provides CPU-level benefits such as more efficient instruction decoding, better stack pointer tracking, and improved register dependency management. Their uniform encoding allows for streamlined execution, reduced pipeline stalls, and potential micro-op fusion, all of which enhance performance and power efficiency. This pairing helps the processor optimize speculative execution and register lifetimes, making code faster and more scalable on modern architectures.
>
> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
> 
>   change to push_ppx/pop_ppx

src/hotspot/cpu/x86/macroAssembler_x86.cpp line 806:

> 804: }
> 805: 
> 806: void MacroAssembler::pop_ppx(Register dst) {

Hi @vamsi-parasa , If you rename pop_ppx to pop and push_ppx to push, it will cut down the changes in this patch significantly.

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PR Review Comment: https://git.openjdk.org/jdk/pull/25889#discussion_r2213907529