RFR: 8359435: AArch64: add support for 8.5 SB instruction

[Aleksey Shipilev]

On Fri, 13 Jun 2025 14:00:08 GMT, Evgeny Astigeevich <eastigeevich at openjdk.org> wrote:

> Speculation Barrier (SB) instruction can be used instead of a pair of DSB, ISB if supported. It should have better performance than DSB+ISB (https://developer.arm.com/documentation/102825/0100):
> 
>> ... a DSB+ISB sequence is expected to have a significantly greater impact on performance than an SB ...
> 
> CPUs supporting it:
> - Apple M2+
> - Neoverse-N2
> - Neoverse-V2
> 
> Tested:
> - Gtests passed

FWIW, I don't mind the SB assembler support to go under this, separate PR. We sometimes do it to split the work in the series of atomic commits, where the commit like this should certainly be non-regressing. The actual use of SB (spin-pauses) can then come under separate RFE, and would require much more work (and have associated risk).

So, it would be tad less confusing if we had a dependent RFE for using SB in spin pauses, so it was obvious why do we need it.

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PR Comment: https://git.openjdk.org/jdk/pull/25801#issuecomment-2970996306