RFR: 8349632: RISC-V: Add Zfa fminm/fmaxm

[Anjian Wen]

On Fri, 21 Feb 2025 04:03:11 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Add RISCV zfa extension fminm/fmaxm
>> This two new Floating-point instructions can deal with NaN input directly, which can decrease instructions when calculate min or max
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2161:
> 
>> 2159: void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
>> 2160:                                   bool is_double, bool is_min) {
>> 2161:   assert_different_registers(dst, src1, src2);
> 
> Do FMINM.S and FMAXM.S have a constraint on the registers?

Thanks for replying. 
>From Zfa doc https://github.com/riscv/riscv-isa-manual/blob/main/src/zfa.adoc, FMINM.S/FMAXM.S look defined like the FMIN.S and FMAX.S instructions. And from the ISA manual, I have not found any constraints on the registers. it only needs normal floating point registers

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PR Review Comment: https://git.openjdk.org/jdk/pull/23509#discussion_r1964905518