RFR: 8349632: RISC-V: Add Zfa fminm/fmaxm

[Fei Yang]

On Fri, 7 Feb 2025 06:52:13 GMT, Anjian Wen <duke at openjdk.org> wrote:

> Add RISCV zfa extension fminm/fmaxm
> This two new Floating-point instructions can deal with NaN input directly, which can decrease instructions when calculate min or max

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2159:

> 2157: }
> 2158: 
> 2159: void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,

There is no need to have this macro-assembler routine. You can call `fminm_s/d` / `fmaxm_s/d` directly on the callsites.

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2161:

> 2159: void C2_MacroAssembler::minmmaxm_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
> 2160:                                   bool is_double, bool is_min) {
> 2161:   assert_different_registers(dst, src1, src2);

Do FMINM.S and FMAXM.S have a constraint on the registers?

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PR Review Comment: https://git.openjdk.org/jdk/pull/23509#discussion_r1966377744
PR Review Comment: https://git.openjdk.org/jdk/pull/23509#discussion_r1964799700