RFR: 8355699: RISC-V: support SUADD/SADD/SUSUB/SSUB

[Fei Yang]

On Fri, 2 May 2025 12:19:53 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review this patch to add SUADD/SADD/SUSUB/SSUB for vector api?
> 
> Thanks!
> 
> ## Test
> 
> running in progress ...

Seems OK. I only have one minor comment.

src/hotspot/cpu/riscv/riscv_v.ad line 696:

> 694:   match(Set dst_src (SaturatingAddV (Binary dst_src src1) v0));
> 695:   ins_cost(VEC_COST);
> 696:   format %{ "vsadd_masked $dst_src, $dst_src, $src1" %}

Nit: Seems the mask register (`v0`) is missing in opto asm for these masked operations.
For integrity, we always print the mask register as the last operand for other masked nodes. 
`format %{ "vsadd_masked $dst_src, $dst_src, $src1, $v0" %}`

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PR Review: https://git.openjdk.org/jdk/pull/25005#pullrequestreview-2814374168
PR Review Comment: https://git.openjdk.org/jdk/pull/25005#discussion_r2073190452