RFR: 8355585: Aarch64: Add aarch64 backend for Float16 vector operations

[Andrew Haley]

On Mon, 12 May 2025 06:37:13 GMT, Xiaohong Gong <xgong at openjdk.org> wrote:

>> This patch adds aarch64 backend (both Neon and SVE) for FP16 vector operations - add, mul, sub, div, min, max, sqrt and fma.
>> 
>> Testing:
>> JTREG tests - hotspot_all, jdk (tier 1-3) and langtools (tier 1) pass on aarch64 which also includes the JTREG test to test the FP16 vector operations - `test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorOperations.java`
>
> src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 2749:
> 
>> 2747:   void adv_simd_three_same(Instruction_aarch64 &current_insn, FloatRegister Vd,
>> 2748:                            SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm,
>> 2749:                            int op1, int op2, int op3);
> 
> May I ask why you move this to the .cpp file?

It's not a bad thing to do. Once the function gets so large, especially when it is inlined many times, that's a wise thing to do.

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PR Review Comment: https://git.openjdk.org/jdk/pull/25096#discussion_r2084038897