RFR: 8355585: Aarch64: Add aarch64 backend for Float16 vector operations

[Bhavana Kilambi]

On Mon, 12 May 2025 06:43:33 GMT, Xiaohong Gong <xgong at openjdk.org> wrote:

>> This patch adds aarch64 backend (both Neon and SVE) for FP16 vector operations - add, mul, sub, div, min, max, sqrt and fma.
>> 
>> Testing:
>> JTREG tests - hotspot_all, jdk (tier 1-3) and langtools (tier 1) pass on aarch64 which also includes the JTREG test to test the FP16 vector operations - `test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorOperations.java`
>
> src/hotspot/cpu/aarch64/aarch64_vector.ad line 698:
> 
>> 696: instruct vaddHF_masked(vReg dst_src1, vReg src2, pRegGov pg) %{
>> 697:   predicate(UseSVE > 0);
>> 698:   match(Set dst_src1 (AddVHF (Binary dst_src1 src2) pg));
> 
> Do we have such a case in existing jtreg now?

Not at the moment. Thanks for pointing this out. I think for this PR, I will remove the predicated instructions support and for now only keep support for non-masked ones. I will add this support when there will be more focus on the masked versions once VectorAPI with Float16Vector is integrated with mainline. Hope this is ok.

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PR Review Comment: https://git.openjdk.org/jdk/pull/25096#discussion_r2084165085