RFR: 8355585: Aarch64: Add aarch64 backend for Float16 vector operations

[Xiaohong Gong]

On Mon, 12 May 2025 08:48:26 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64_vector.ad line 698:
>> 
>>> 696: instruct vaddHF_masked(vReg dst_src1, vReg src2, pRegGov pg) %{
>>> 697:   predicate(UseSVE > 0);
>>> 698:   match(Set dst_src1 (AddVHF (Binary dst_src1 src2) pg));
>> 
>> Do we have such a case in existing jtreg now?
>
> Not at the moment. Thanks for pointing this out. I think for this PR, I will remove the predicated instructions support and for now only keep support for non-masked ones. I will add this support when there will be more focus on the masked versions once VectorAPI with Float16Vector is integrated with mainline. Hope this is ok.

Sounds good to me. But I'm worried it may crash with bad ad file on AArch64 if the Vector API java and compiler IR part is ready for HF types, while the AArch64 relative masked rules are missing.  Beacause the masked vector IR have been generated, while the codegen is missing on AArch64. We have to add the HF ops to `match_rule_supported_vector_masked` first, and then remove them when adding the masked version rules. WDYT?

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PR Review Comment: https://git.openjdk.org/jdk/pull/25096#discussion_r2084182434