RFR: 8357056: RISC-V: Asm fixes - load/store width

[Fei Yang]

On Thu, 15 May 2025 14:46:12 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

> Hi, please consider.
> 
> While working on https://github.com/openjdk/jdk/pull/25252, I notice:
> - Major op code was just repeat
> - Width coded in binary
> - Stores have mixed up rs1 and rs2
> - Bonus, fsd used a macro for no reason
> 
> I think this improves readability.
> 
> Tested tier1
> 
> Thanks, Robbin

Nice cleanup! Thanks.

src/hotspot/cpu/riscv/assembler_riscv.hpp line 730:

> 728:   void _ld(Register Rd, Register Rs, const int32_t offset) {
> 729:     load_base<LOAD_WIDTH_DOUBLEWORD>(Rd, Rs, offset);
> 730:   }

Question: Can we refactor and move definition of `flh`, `flw` and `fld` here?
The definition of `fp_load` [1] looks quite similar as `load_base` here.

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/assembler_riscv.hpp#L1352

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PR Review: https://git.openjdk.org/jdk/pull/25253#pullrequestreview-2852297912
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2096692780