RFR: 8357056: RISC-V: Asm fixes - load/store width [v2]

[Robbin Ehn]

On Tue, 20 May 2025 01:33:33 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision:
>> 
>>  - Fixed flh/flw/fld
>>  - Merge branch 'master' into asm_fixes
>>  - Fixes
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 730:
> 
>> 728:   void _ld(Register Rd, Register Rs, const int32_t offset) {
>> 729:     load_base<LOAD_WIDTH_DOUBLEWORD>(Rd, Rs, offset);
>> 730:   }
> 
> Question: Can we refactor and define `flh`, `flw` and `fld` with this `load_base` as well?
> The definition of `fp_load` [1] looks quite similar as `load_base` here, so it could be factored out.
> 
> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/assembler_riscv.hpp#L1352

Fixed !

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PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2097768887