RFR: 8357056: RISC-V: Asm fixes - load/store width [v2]

[Robbin Ehn]

On Wed, 21 May 2025 08:36:09 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision:
>> 
>>  - Fixed flh/flw/fld
>>  - Merge branch 'master' into asm_fixes
>>  - Fixes
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 3307:
> 
>> 3305: 
>> 3306: // --------------------------
>> 3307:   void sd(Register Rd, Register Rs, const int32_t offset) {
> 
> We can rename `Rd`/`Rs` to `Rs2`/`Rs1` to be more consistent with the specification.

Fixed

> src/hotspot/cpu/riscv/assembler_riscv.hpp line 3322:
> 
>> 3320: 
>> 3321: // --------------------------
>> 3322:   void sw(Register Rd, Register Rs, const int32_t offset) {
> 
> Same here.

Fixed

> src/hotspot/cpu/riscv/assembler_riscv.hpp line 3337:
> 
>> 3335: 
>> 3336: // --------------------------
>> 3337:   void fsd(FloatRegister Rd, Register Rs, const int32_t offset) {
> 
> And here.

Fixed

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2101847874
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2101848112
PR Review Comment: https://git.openjdk.org/jdk/pull/25253#discussion_r2101848338