RFR: 8360654: AArch64: Remove redundant dmb from C1 compareAndSet [v5]

[Andrew Haley]

On Wed, 12 Nov 2025 11:15:03 GMT, Samuel Chee <duke at openjdk.org> wrote:

>> AtomicLong.CompareAndSet has the following assembly dump snippet which gets emitted from the intermediary LIRGenerator::atomic_cmpxchg:
>> 
>> ;; cmpxchg {
>>   0x0000e708d144cf60:   mov	x8, x2
>>   0x0000e708d144cf64:   casal	x8, x3, [x0]
>>   0x0000e708d144cf68:   cmp	x8, x2
>>  ;; 0x1F1F1F1F1F1F1F1F
>>   0x0000e708d144cf6c:   mov	x8, #0x1f1f1f1f1f1f1f1f
>>  ;; } cmpxchg
>>   0x0000e708d144cf70:   cset	x8, ne  // ne = any
>>   0x0000e708d144cf74:   dmb	ish
>> 
>> 
>> According to the Oracle Java Specification, AtomicLong.CompareAndSet [1] has the same memory effects as specified by VarHandle.compareAndSet which has the following effects: [2]
>> 
>>> Atomically sets the value of a variable to the
>>> newValue with the memory semantics of setVolatile if
>>> the variable's current value, referred to as the witness
>>> value, == the expectedValue, as accessed with the memory
>>> semantics of getVolatile.
>> 
>> 
>> 
>> Hence the release on the store due to setVolatile only occurs if the compare is successful. Since casal already satisfies these requirements, the dmb does not need to occur to ensure memory ordering in case the compare fails and a release does not happen.
>> 
>> Hence we remove the dmb from both casl and casw (same logic applies to the non-long variant)
>> 
>> This is also reflected by C2 not having a dmb for the same respective method.
>> 
>> [1] https://docs.oracle.com/en/java/javase/24/docs/api/java.base/java/util/concurrent/atomic/AtomicLong.html#compareAndSet(long,long)
>> [2] https://docs.oracle.com/en/java/javase/24/docs/api/java.base/java/lang/invoke/VarHandle.html#compareAndSet(java.lang.Object...)
>
> Samuel Chee has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains six additional commits since the last revision:
> 
>  - Address review comments. Refine.
>  - Merge from the main branch
>  - Add cmpxchg_barrier helper
>    
>    Change-Id: I17acf999140f0c1decb256de8291361c568a4ff8
>  - Add comment
>    
>    Signed-off-by: Samuel Chee <samche01 at arm.com>
>    Change-Id: I9793ed6ffdff6c044552d069af23620d178f2284
>  - Add back in dmb membar for non-LSE
>    
>    Change-Id: Ie64565420a1758d3191eaebed82c80584ce54ef6
>  - 8360654: AArch64: Remove redundant dmb from C1 compareAndSet
>    
>    Change-Id: I79a0079fc2d3d90eeb671b6ed73d963968d4fa53

src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp line 3471:

> 3469:                              bool weak,
> 3470:                              Register result) {
> 3471:   cmpxchg(addr, expected, new_val, size, acquire, release, weak, result, false);

Suggestion:

  cmpxchg(addr, expected, new_val, size, acquire, release, weak, result, /*with_barrier*/false);

Reason: avoid naked booleans at call sites.
Please do this everywhere.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/26000#discussion_r2518449445