RFR: 8366076: arm32: Fix register allocation for vector instructions

[Dean Long]

On Sun, 16 Nov 2025 22:55:24 GMT, Max Verevkin <duke at openjdk.org> wrote:

>> src/hotspot/cpu/arm/arm_32.ad line 330:
>> 
>>> 328:                       R_S16,R_S17,R_S18,R_S19, R_S20,R_S21,R_S22,R_S23,
>>> 329:                       R_S24,R_S25,R_S26,R_S27, R_S28,R_S29,R_S30,R_S31);
>>> 330: 
>> 
>> Isn't this the same as dflt_low_reg?
>
> I am not 100% sure if they are completely equivalent and `dflt_low_reg` could be used instead of defining a new class. I figured I should introduce a new class similar to how `sflt_reg` and `dflt_low_reg` are similar yet distinct.

A reg_class just produces a RegMask, so there is no need to give identical masks different names.  Aliasing can still be done.  See `actual_dflt_reg` for example.

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PR Review Comment: https://git.openjdk.org/jdk/pull/27071#discussion_r2536349196