RFR: 8366076: arm32: Fix register allocation for vector instructions

[Max Verevkin]

On Fri, 14 Nov 2025 02:34:48 GMT, Dean Long <dlong at openjdk.org> wrote:

>> Arm32 has 32 double-precision floating point registers, the first 16 of which coincide with the 32 single-precision floating point registers. Some vector-operation nodes were implemented in terms of scalar instructions, which only really works for the first 16 doubles. This commit addresses that.
>
> src/hotspot/cpu/arm/arm_32.ad line 330:
> 
>> 328:                       R_S16,R_S17,R_S18,R_S19, R_S20,R_S21,R_S22,R_S23,
>> 329:                       R_S24,R_S25,R_S26,R_S27, R_S28,R_S29,R_S30,R_S31);
>> 330: 
> 
> Isn't this the same as dflt_low_reg?

I am not 100% sure if they are completely equivalent and `dflt_low_reg` could be used instead of defining a new class. I figured I should introduce a new class similar to how `sflt_reg` and `dflt_low_reg` are similar yet distinct.

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PR Review Comment: https://git.openjdk.org/jdk/pull/27071#discussion_r2532299653