RFR: 8371968: RISC-V: implement AES CBC intrinsics

[Fei Yang]

On Fri, 14 Nov 2025 11:30:41 GMT, Anjian Wen <wenanjian at openjdk.org> wrote:

> Support AES CBC intrinsic on RISCV, Already passed the tests in
> test/hotspot/jtreg/compiler/codegen/aes/
> test/jdk/com/sun/crypto

Hi, Thanks for making the changes. I am having a look.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2619:

> 2617:   //
> 2618:   // Output:
> 2619:   //   x0        - input length

Shouldn't this be `x10`? `x0` is the zero register on riscv.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2727:

> 2725:   //
> 2726:   // Output:
> 2727:   //   r0        - input length

Same question here.

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PR Review: https://git.openjdk.org/jdk/pull/28320#pullrequestreview-3509268954
PR Review Comment: https://git.openjdk.org/jdk/pull/28320#discussion_r2563600347
PR Review Comment: https://git.openjdk.org/jdk/pull/28320#discussion_r2563602419