RFR: 8371968: RISC-V: implement AES CBC intrinsics [v2]

[Anjian Wen]

On Wed, 26 Nov 2025 07:03:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Anjian Wen has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   fix some comments
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2619:
> 
>> 2617:   //
>> 2618:   // Output:
>> 2619:   //   x0        - input length
> 
> Shouldn't this be `x10`? `x0` is the zero register on riscv.

Thanks for the reminder, fixed!

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PR Review Comment: https://git.openjdk.org/jdk/pull/28320#discussion_r2566996650