RFR: 8365732: RISC-V: implement AES CTR intrinsics [v11]

[Anjian Wen]

On Sat, 18 Oct 2025 12:05:50 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Anjian Wen has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 12 commits:
>> 
>>  - Merge branch 'openjdk:master' into aes_ctr
>>  - add assertion and change test
>>  - add zbb and zvbb check
>>  - Merge branch 'openjdk:master' into aes_ctr
>>  - Merge branch 'openjdk:master' into aes_ctr
>>  - fix the counter increase at limit and add test
>>  - change format
>>  - update reg use and instruction
>>  - change some name and format
>>  - delete useless Label, change L_judge_used to L_slow_loop
>>  - ... and 2 more: https://git.openjdk.org/jdk/compare/eff6439e...716825a4
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2626:
> 
>> 2624:   //
>> 2625:   address generate_counterMode_AESCrypt() {
>> 2626:     assert(UseAESCTRIntrinsics, "need AES instructions (Zvkned extension) support");
> 
> It's hard for anyone to understand the control flow. If you look at the same routine in the AArch64 port you'll see plenty of comments to help the reader.

Thanks,  I'll try to add some more comments and maybe a pseudocode about my control flow refer to aarch64

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2443904661