RFR: 8365732: RISC-V: implement AES CTR intrinsics [v11]

[Anjian Wen]

On Mon, 20 Oct 2025 09:40:29 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> @theRealAph Sorry, I don't quite understand what the "constant time" here means.
>> 
>> if you mean counter increase, here I try to optimize counter increase with vectorAdd. If N is the number of counter we should increase, it can theoretically optimize the time use from `O(N * 16) `to `O(N * 2 / (4 * (vector_register_len / 64)))`, as for vector_register_len equals 128, it will optimize about 64 times if the N is large enough.
>
> And I don't understand any of that.
> 
> You should follow the example of the other implementations of CTR mode in HotSpot, so that no matter what the value of the counter is, incrementing it takes the same time.

@theRealAph 
1. Here I mean increase more than one counter the same time, because we can set LMUL more than 1 in RISCV. And for the vector register len (VLEN)in riscv is not a constant value we can not assume the number of counter we can deal once a time.

2. I have not found a suitable  overflow check in riscv RVV, so I use pre check to avoid overflow, here we may discuss is there a more suitable way. 

3. Why we should make the counter increment same time? Why is this necessary?

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PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2444522378