RFR: 8365732: RISC-V: implement AES CTR intrinsics [v11]

[Andrew Haley]

On Mon, 20 Oct 2025 10:05:21 GMT, Anjian Wen <wenanjian at openjdk.org> wrote:

> * I have not found a suitable  overflow check in riscv RVV, so I use pre check to avoid overflow, here we may discuss is there a more suitable way.

Sure, OK.

> * Why we should make the counter increment same time? Why is this necessary?

Because we don't want to leak any information about the internal state of the cipher to an observer. You must assume that an observer can precisely measure execution time, power consumption, and so on.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/25281#discussion_r2451088474