RFR: 8359378: aarch64: crash when using -XX:+UseFPUForSpilling

[Andrew Haley]

On Wed, 17 Sep 2025 16:19:12 GMT, Boris Ulasevich <bulasevich at openjdk.org> wrote:

> AArch64 BarrierSetAssembler path assumes only FP/vector ideal regs reach the FP spill/restore encoding. With -XX:+UseFPUForSpilling Register Allocator may allocate scalar values in FP registers. When such values (Op_RegI/Op_RegN/Op_RegL/Op_RegP) hit `BarrierSetAssembler::encode_float_vector_register_size`, we trip ShouldNotReachHere in release build and **"unexpected ideal register"** assertion in debug build.
> 
> Fix: teach the encoder to handle scalar ideal regs when they physically live in FP regs:
> - treat Op_RegI / Op_RegN as 32-bit (single slot) - same class as Op_RegF
> - treat Op_RegL / Op_RegP as 64-bit (two slots) - same class as Op_RegD
> 
> Related:
> - reproduced since #19746
> - spilling logic: 
>   - #18967
>   - #17977
> 
> Testing: tier1-3 with javaoptions -Xcomp -Xbatch -XX:+UseFPUForSpilling on AARCH

Given that you're looking at this, I'd appreciate it if you could form an opinion bout whether this option is of any use.

`UseFPUForSpilling` on AArch64 is showing signs of code rot. If it has advantages on some machine we should turn it on by default; if it does not, why support it at all?

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PR Comment: https://git.openjdk.org/jdk/pull/27350#issuecomment-3306800418