Presentation: Understanding OrderAccess
martin.doerr at sap.com
Wed Nov 23 16:20:32 UTC 2016
thank you very much for the presentation. I think it provides a good guideline for hotspot development.
Would you like to add something about multi-copy atomicity?
E.g. there's a usage of OrderAccess::fence() in GenericTaskQueue<E, F, N>::pop_global which is only needed on platforms which don't provide this property (PPC and ARM).
It is needed in the following scenario:
- Different threads write 2 variables.
- Readers of these 2 variables expect a globally consistent order of the write accesses.
In this case, the readers must use OrderAccess::fence() between the 2 load accesses on platforms without "multi-copy atomicity".
(While taking a look at it, the condition "#if !(defined SPARC || defined IA32 || defined AMD64)" is not accurate and should better get improved. E.g. s390 is multi-copy atomic.)
I like that you have added our cmpxchg_memory_order definition. We implemented it even more conservative than C++' seq_cst on PPC64.
Thanks and best regards,
From: hotspot-dev [mailto:hotspot-dev-bounces at openjdk.java.net] On Behalf Of David Holmes
Sent: Mittwoch, 23. November 2016 06:08
To: hotspot-dev developers <hotspot-dev at openjdk.java.net>
Subject: Presentation: Understanding OrderAccess
This is a presentation I recently gave internally to the runtime and serviceability teams that may be of more general interest to hotspot developers.
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