Presentation: Understanding OrderAccess

David Holmes david.holmes at
Mon Nov 28 05:55:35 UTC 2016

Hi Martin

On 24/11/2016 2:20 AM, Doerr, Martin wrote:
> Hi David,
> thank you very much for the presentation. I think it provides a good guideline for hotspot development.


> Would you like to add something about multi-copy atomicity?

Not really. :)

> E.g. there's a usage of OrderAccess::fence() in GenericTaskQueue<E, F, N>::pop_global which is only needed on platforms which don't provide this property (PPC and ARM).
> It is needed in the following scenario:
> - Different threads write 2 variables.
> - Readers of these 2 variables expect a globally consistent order of the write accesses.
> In this case, the readers must use OrderAccess::fence() between the 2 load accesses on platforms without "multi-copy atomicity".

Hmmm ... I know this code was discussed at length a couple of years ago 
... and I know I've probably forgotten most of what was discussed ... so 
I'll have to revisit this because this seems wrong ...

> (While taking a look at it, the condition "#if !(defined SPARC || defined IA32 || defined AMD64)" is not accurate and should better get improved. E.g. s390 is multi-copy atomic.)
> I like that you have added our cmpxchg_memory_order definition. We implemented it even more conservative than C++' seq_cst on PPC64.

I still can't get my head around the C++11 terminology for this and how 
you are expected to use it - what does it mean for an individual 
operation to be "sequentially consistent" ? :(


> Thanks and best regards,
> Martin
> -----Original Message-----
> From: hotspot-dev [mailto:hotspot-dev-bounces at] On Behalf Of David Holmes
> Sent: Mittwoch, 23. November 2016 06:08
> To: hotspot-dev developers <hotspot-dev at>
> Subject: Presentation: Understanding OrderAccess
> This is a presentation I recently gave internally to the runtime and serviceability teams that may be of more general interest to hotspot developers.
> Cheers,
> David

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