RFR: AArch64: 8179954: AArch64: C1 and C2 volatile accesses are not sequentially consistent

[David Holmes]

Hi Andrew,

On 10/05/2017 3:18 AM, Andrew Haley wrote:
> In C2 we use LDAR/STLR to handle volatile accesses, but in C1 and the
> interpreter we use separate DMB instructions and relaxed loads. When
> used together, these do not form a sequentially-consistent memory
> ordering. For example, if stores use STLR and loads use LDR;DMB a
> simple Dekker idiom will fail.

I'm somewhat confused by this description. Outside of Aarch64 the 
general approach, for C1 and Unsafe at least, is that a volatile-read is 
a load-acquire() (or a fence-load-acquire if you want the IRIW support) 
and a volatile write is a release-store-fence (or just release-store 
with IRIW support). Does Aarch64 not follow this pattern?

I'm trying to see if the issue here is the original code generation or a 
subtle incompatibility between the ld-acq/st-rel instructions and 
explicit DMB.

Thanks,
David

> This is extremely hard to test because the loads and stores have to be
> in separately-compiled methods, but it is incorrect, and likely to
> fail in very weakly-ordered implementations.
>
> Note: this is for JDK 9.
>
>  http://cr.openjdk.java.net/~aph/8179954/
>
> Andrew.
>