RFR: 8274179: AArch64: Support SVE operations with encodable immediates

[Andrew Haley]

On Tue, 26 Oct 2021 01:58:40 GMT, Fei Gao <duke at openjdk.java.net> wrote:

> for(int i = 0; i < LENGTH; i++) {
>       c[i] = a[i] + 2;
>     }
> 
> For the case showed above, after superword optimization with SVE,
> without the patch, the vector add operation always has 2 z-reg inputs,
> like:
> mov     z16.s, #2
> add	z17.s, z17.s, z16.s
> 
> Considering sve has supported basic binary operations with immediate,
> this pattern could be further optimized to:
> add     z16.s, z16.s, #2
> 
> To implement it, we added some new match rules and assembler rules in
> the aarch64 backend. We also made some extensions on immediate types
> and functions to keep backward compatible.
> 
> With the patch, only these binary integer vector operations, +(add),
> -(sub), &(and), |(orr), and ^(eor) with immediate are supported for
> the optimization. Other vector operations are not supported currently.
> 
> Tested tier1 and test/hotspot/jtreg/compiler on SVE featured AArch64
> CPU, no new failure.
> 
> There is no obvious performance uplift but it can help remove one
> redundant mov instruction.

src/hotspot/cpu/aarch64/aarch64.ad line 2669:

> 2667:   if (!imm_node->is_Con() ||
> 2668:       !(imm_node->bottom_type()->isa_int() || imm_node->bottom_type()->isa_long())) {
> 2669:     return false;

I'd split this up a bit.

Please consider


if (!imm_node->is_Con()  return false;

const Type t = imm_node->bottom_type();
if (! (t->isa_int() || t->isa_long))  return false;

-------------

PR: https://git.openjdk.java.net/jdk/pull/6115