RFR: 8274179: AArch64: Support SVE operations with encodable immediates [v3]

[Andrew Haley]

On Thu, 28 Oct 2021 10:43:33 GMT, Fei Gao <duke at openjdk.java.net> wrote:

>> for(int i = 0; i < LENGTH; i++) {
>>       c[i] = a[i] + 2;
>>     }
>> 
>> For the case showed above, after superword optimization with SVE,
>> without the patch, the vector add operation always has 2 z-reg inputs,
>> like:
>> mov     z16.s, #2
>> add	z17.s, z17.s, z16.s
>> 
>> Considering sve has supported basic binary operations with immediate,
>> this pattern could be further optimized to:
>> add     z16.s, z16.s, #2
>> 
>> To implement it, we added some new match rules and assembler rules in
>> the aarch64 backend. We also made some extensions on immediate types
>> and functions to keep backward compatible.
>> 
>> With the patch, only these binary integer vector operations, +(add),
>> -(sub), &(and), |(orr), and ^(eor) with immediate are supported for
>> the optimization. Other vector operations are not supported currently.
>> 
>> Tested tier1 and test/hotspot/jtreg/compiler on SVE featured AArch64
>> CPU, no new failure.
>> 
>> There is no obvious performance uplift but it can help remove one
>> redundant mov instruction.
>
> Fei Gao has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.

Looks fine with those minor changes.

src/hotspot/cpu/aarch64/assembler_aarch64.cpp line 86:

> 84: 
> 85: unsigned Assembler::regVariant_to_elemBits(Assembler::SIMD_RegVariant T){
> 86:   return 1 << (T + 3);

Assert something about `T` here.

src/hotspot/cpu/aarch64/assembler_aarch64.cpp line 394:

> 392:   if (uimm < (UCONST64(1) << nbits))
> 393:     return true;
> 394:   if (uimm < (UCONST64(1) << (2 * nbits))

Assert something about `nbits` here. It has to be less than 32, I think.

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PR: https://git.openjdk.java.net/jdk/pull/6115