RFR: 8274179: AArch64: Support SVE operations with encodable immediates [v3]

[Fei Gao]

On Thu, 28 Oct 2021 11:46:58 GMT, Andrew Haley <aph at openjdk.org> wrote:

>> Fei Gao has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
>
> src/hotspot/cpu/aarch64/assembler_aarch64.cpp line 86:
> 
>> 84: 
>> 85: unsigned Assembler::regVariant_to_elemBits(Assembler::SIMD_RegVariant T){
>> 86:   return 1 << (T + 3);
> 
> Assert something about `T` here.

Done

> src/hotspot/cpu/aarch64/assembler_aarch64.cpp line 394:
> 
>> 392:   if (uimm < (UCONST64(1) << nbits))
>> 393:     return true;
>> 394:   if (uimm < (UCONST64(1) << (2 * nbits))
> 
> Assert something about `nbits` here. It has to be less than 32, I think.

Done

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PR: https://git.openjdk.java.net/jdk/pull/6115