RFR: 8291302: ARM32: nmethod entry barriers support [v3]

[Aleksei Voitylov]

On Thu, 1 Dec 2022 08:09:29 GMT, Richard Reingruber <rrich at openjdk.org> wrote:

>> Aleksei Voitylov has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   remove membar
>
> src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp line 221:
> 
>> 219:   // Subsequent loads of oops must occur after load of guard value.
>> 220:   // BarrierSetNMethod::disarm sets guard with release semantics.
>> 221:   __ membar(MacroAssembler::LoadLoad, tmp1);
> 
> Is my assumption correct that ARM32 supports neither ZGC nor ShenandoahGC?
> If so then no memory barrier is needed as no oops are modified concurrently with G1 (and other GCs are not concurrent).
> I'd recomment to implement `BarrierSetAssembler::nmethod_patching_type()` as on AARCH64 and replace the membar with an assertion that `NMethodPatchingType::stw_instruction_and_data_patch` is in effect.
> @fisk wouldn't it be good if there was a shared method to query if oops (other values?) are modified concurrently?

The membar is now removed.

-------------

PR: https://git.openjdk.org/jdk/pull/11442