RFR: 8291302: ARM32: nmethod entry barriers support [v3]

[Dmitry Samersoff]

On Mon, 5 Dec 2022 16:24:09 GMT, Aleksei Voitylov <avoitylov at openjdk.org> wrote:

>> src/hotspot/cpu/arm/gc/shared/barrierSetAssembler_arm.cpp line 221:
>> 
>>> 219:   // Subsequent loads of oops must occur after load of guard value.
>>> 220:   // BarrierSetNMethod::disarm sets guard with release semantics.
>>> 221:   __ membar(MacroAssembler::LoadLoad, tmp1);
>> 
>> Is my assumption correct that ARM32 supports neither ZGC nor ShenandoahGC?
>> If so then no memory barrier is needed as no oops are modified concurrently with G1 (and other GCs are not concurrent).
>> I'd recomment to implement `BarrierSetAssembler::nmethod_patching_type()` as on AARCH64 and replace the membar with an assertion that `NMethodPatchingType::stw_instruction_and_data_patch` is in effect.
>> @fisk wouldn't it be good if there was a shared method to query if oops (other values?) are modified concurrently?
>
> The membar is now removed.

I'm second to the proposal to move nmethod_patching_type() to shared code.

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PR: https://git.openjdk.org/jdk/pull/11442