RFR: 8280867: Cpuid1Ecx feature parsing is incorrect for AMD CPUs

[Vladimir Kozlov]

On Mon, 31 Jan 2022 11:26:29 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

> See discussion in the bug. AFAICS, the fix is to "just" shift the flags by one to match both Intel and AMD specs. I believe this is not a serious bug, because adjacent bits in AMD case are set on modern chips, and Intel detection code only uses `lzcnt` and `prefetchw` out of these flags, both with Intel-specific hacks that are dropped now.
> 
> Additional testing:
>  - [x] Linux x86_64 fastdebug on TR 3970X (Zen 2)
>  - [x]  Linux x86_64 fastdebug on i5-11500 (Rocket Lake)
>  - [x] Eyeballing `-Xlog:os+cpu` on TR 3970X (Zen 2) -- no change in detected flags
>  - [x]  Eyeballing `-Xlog:os+cpu` on i5-11500 (Rocket Lake) -- no change in detected flags

Right. In Intel's manual:

CPUID.(EAX=8000_0001H):ECX[bit 5]=1 indicates LZCNT is supported.
CPUID.(EAX=8000_0001H):ECX[bit 8]=1 indicates PREFETCHW is supported.


>From AMD's

ECX[bit 5]=1 ABM: advanced bit manipulation. LZCNT instruction support.
ECX[bit 6]=1 SSE4A: EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support.
ECX[bit 7]=1 MisAlignSse: misaligned SSE mode.
ECX[bit 8]=1 3DNowPrefetch: PREFETCH and PREFETCHW instruction support.

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Marked as reviewed by kvn (Reviewer).

PR: https://git.openjdk.java.net/jdk/pull/7287