RFR: JDK-8290137: riscv: small refactoring for add_memory_int32/64

[Yadong Wang]

On Tue, 12 Jul 2022 08:14:05 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Currently, add_memory_int32/64 for riscv can only add a sign-extended 12-bit immediate to memory since they call addi/addiw assembler direcly. This constraint could be relaxed when the given memory address is in the expected form: base register plus a sign-extended 12-bit offset. In this case, we can emit code for load + add/sub + store sequence adding arbitrary immediate to memory with no more than two scratch registers (t0 and t1) available.
> 
> We could also refactor these two functions into four seperate functions: increment, incrementw, decrement and decrementw, so that it will be more clear in code logic at the call sites.
> 
> Test: hotspot-tier1 & jdk-tier1 with QEMU.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 2965:

> 2963:   assert(!adr.uses(t0), "invalid dst for address increment");
> 2964:   ld(t0, adr);
> 2965:   add(t0, t0, value, t1);

It's not safe to clobber t1 sometimes. And I think it's better to limit the accepted value to 12 bits or less.

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PR: https://git.openjdk.org/jdk/pull/9461