RFR: 8290280: riscv: Clean up stack and register handling in interpreter

[Fei Yang]

On Thu, 14 Jul 2022 07:42:57 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> As [JDK-8288971](https://bugs.openjdk.org/browse/JDK-8288971) described, we have the same issue on riscv backend:
> 
> 1. We use x30 to pass the caller's SP to a callee through adapters. x30 is not a callee-saved register in native ABI [1], we choose x19 for this patch.
> 2. We frequently recalculate the location where the native SP needs to go. We have a spare slot in the interpreter frame, so we should calculate it once, when the frame is created, and use it.
> 3. Relate to 1, we should clearly label all the places where the caller's SP is passed to a callee.
> 
> [1]. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
> 
> Additional tests:
> - hotspot/jdk tier1 on  QEMU with Release JDK
> - hotspot tier1 on HiFive Unmatched board with Release JDK
> - hotspot tier1 on QEMU with Fastdebug JDK

Changes requested by fyang (Reviewer).

src/hotspot/cpu/riscv/interp_masm_riscv.hpp line 96:

> 94:   }
> 95: 
> 96:   void check_extended_sp(const char* msg =  "check extended SP") {

Redundant space in RHS of assignment.

src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 709:

> 707:   __ add(esp, esp, - entry_size);
> 708:   __ mv(t0, sp);
> 709:   __ sd(t0, Address(fp, frame::interpreter_frame_extended_sp_offset * wordSize));

Why not store sp directly here? Looks like use of t0 here is not necessary.

src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 779:

> 777:     __ sub(t0, sp, t0);
> 778:     __ andi(t0, t0, -16);
> 779:     // Store extender SP and mirror

typo here: should be "extended" instead of "extender".

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PR: https://git.openjdk.org/jdk/pull/9487