RFR: 8290280: riscv: Clean up stack and register handling in interpreter [v2]

[Feilong Jiang]

On Fri, 15 Jul 2022 07:40:24 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   fix comment and remove unnecessary move sp to t0
>
> Changes requested by fyang (Reviewer).

@RealFYang -- Thank you for the comments! Would you please take another look at the new changes?

> src/hotspot/cpu/riscv/interp_masm_riscv.hpp line 96:
> 
>> 94:   }
>> 95: 
>> 96:   void check_extended_sp(const char* msg =  "check extended SP") {
> 
> Redundant space in RHS of assignment.

Oops, fixed.

> src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 709:
> 
>> 707:   __ add(esp, esp, - entry_size);
>> 708:   __ mv(t0, sp);
>> 709:   __ sd(t0, Address(fp, frame::interpreter_frame_extended_sp_offset * wordSize));
> 
> Why not store sp directly here? Looks like use of t0 here is not necessary.

Yes, we can store sp here directly. The same issue in other places was fixed too.

> src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp line 779:
> 
>> 777:     __ sub(t0, sp, t0);
>> 778:     __ andi(t0, t0, -16);
>> 779:     // Store extender SP and mirror
> 
> typo here: should be "extended" instead of "extender".

Fixed.

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PR: https://git.openjdk.org/jdk/pull/9487