RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V [v2]

[Fei Yang]

On Wed, 2 Nov 2022 08:19:41 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> The OpenJDK supports generating prefetch instructions on most platforms. RISC-V supports through the Zicbop extension the use of prefetch instructions. We want to make sure we use these instructions whenever they are available.
>> 
>> It passes `hotspot:tier1` test suite
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Remove uncessary cache line alignement

src/hotspot/cpu/riscv/riscv.ad line 5196:

> 5194: 
> 5195:   ins_encode %{
> 5196:     __ addi(t0, as_Register($mem$$base), $mem$$disp);

This might be further improved as I see prefetch instructions can receive some immediate offset.

src/hotspot/os_cpu/linux_riscv/prefetch_linux_riscv.inline.hpp line 36:

> 34:         (void (*)(const void*, intptr_t))StubRoutines::riscv::prefetch_r();
> 35:     if (interval >= 0 && stub != NULL) {
> 36:         stub(loc, interval);

I am not sure if it really worth it to call a stub for read / write here. It looks to me not a big issue for the case the stub tries to catch and resolve. And I see aarch64 simply plant a 'prfm' instruction for prefetching [1]. I guess we might can do the same? 

[1] https://github.com/openjdk/jdk/blob/master/src/hotspot/os_cpu/linux_aarch64/prefetch_linux_aarch64.inline.hpp#L34

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PR: https://git.openjdk.org/jdk/pull/10884