RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V [v2]

[Ludovic Henry]

On Wed, 2 Nov 2022 08:52:51 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Remove uncessary cache line alignement
>
> src/hotspot/cpu/riscv/riscv.ad line 5196:
> 
>> 5194: 
>> 5195:   ins_encode %{
>> 5196:     __ addi(t0, as_Register($mem$$base), $mem$$disp);
> 
> This might be further improved as I see prefetch instructions can receive some immediate offset.

The offset needs to be aligned on 32 bytes (the lower 5 bits must be zero). There is then no guarantee that `$mem$$base + ($mem$$disp & ~((1<<5)-1)` is still on the same cache line. It's then easier to do a prefetch of `base+disp` with `offset = 0`.

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PR: https://git.openjdk.org/jdk/pull/10884