RFR: 8286301: Port JEP 425 to RISC-V

[Xiaolin Zheng]

On Wed, 2 Nov 2022 08:51:23 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Hi,
>> 
>> Please review this PR porting JEP 425 (Virtual Threads) to RISC-V.
>> 
>> This is mainly adapted from the work of AArch64 port. Most of the changes lie in RISC-V scope.
>> Changes to HotSpot shared code are trivial and are always guarded by RISCV64 macro. So this won't
>> affect the rest of the world in theory.
>> 
>> There exists some differences in frame structure between AArch64 and RISC-V.
>> For AArch64, we have:
>> 
>> enum {
>>   link_offset           = 0,
>>   return_addr_offset    = 1,
>>   sender_sp_offset      = 2
>> };
>> 
>> While for RISC-V, we have:
>> 
>> enum {
>>   link_offset           = -2,
>>   return_addr_offset    = -1,
>>   sender_sp_offset      =  0
>> };
>> 
>> So we need adapations in some places where the code relies on value of sender_sp_offset to work.
>> Note that implementation for Post-call NOPs optimization is not incorporated in this PR as we plan to
>> evaluate more on its impact on performance.
>> 
>> Testing on Linux-riscv64 HiFive Unmatched board:
>>   - Minimal, Client and Server release & fastdebug build OK.
>>   - Passed tier1-tier4 tests (release build).
>>   - Passed jtreg tests under test/jdk/java/lang/Thread/virtual with extra JVM options: -XX:+VerifyContinuations -XX:+VerifyStack (fastdebug build).
>>   - Performed benchmark tests like Dacapo, SPECjvm2008, SPECjbb2015, etc. to make sure no performance regression are introduced (release build).
>
> src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 979:
> 
>> 977: 
>> 978:     // Make sure the call is patchable
>> 979:     __ align(NativeInstruction::instruction_size);
> 
> alignment was also done in `emit_trampoline_stub`, do we still need this `align` before emitting a trampoline call?

Maybe I can help to answer this question.

This is an RVC-related change.
We want the `call site` itself, which is the `jal` instruction, to be aligned to be patchable, for RVC can make it 2-byte aligned.

[code seg]
    ...
    jal <trampoline start addr>      <---   we are here, and want to force aligning this call site.
    ...


[stub seg]
    ...
<trampoline start addr>:
    auipc
    ld
    jalr
    [64-bit real address]    <-  this is certainly aligned to 8, as you've mentioned.
    ...

-------------

PR: https://git.openjdk.org/jdk/pull/10917