RFR: 8286301: Port JEP 425 to RISC-V [v2]

[Fei Yang]

On Thu, 3 Nov 2022 01:53:11 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Maybe I can help to answer this question.
>> 
>> This is an RVC-related change.
>> We want the `call site` itself, which is the `jal` instruction, to be aligned to be patchable, for RVC can make it 2-byte aligned.
>> 
>> [code seg]
>>     ...
>>     jal <trampoline start addr>      <---   we are here, and want to force aligning this call site.
>>     ...
>> 
>> 
>> [stub seg]
>>     ...
>> <trampoline start addr>:
>>     auipc
>>     ld
>>     jalr
>>     [64-bit real address]    <-  this is certainly aligned to 8, as you've mentioned.
>>     ...
>
> Looks reasonable. As you mentioned that it‘s an RVC-related change, do we need this alignment when `UseRVC` is disabled?

This is necessary to support for RISC-V RVC extension whether it is turned on or off. And I think we are ready to enable use of RVC by default when this hardware extension is available.

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PR: https://git.openjdk.org/jdk/pull/10917