RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V [v6]

[Yadong Wang]

On Mon, 7 Nov 2022 07:26:41 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/riscv.ad line 5202:
>> 
>>> 5200:       __ addi(t0, as_Register($mem$$base), $mem$$disp);
>>> 5201:       __ prefetch_w(t0, 0);
>>> 5202:     }
>> 
>> It'd better to generate the case that handles the imm not fit for instructions like prefetch.w or addi.
>
> I'm not sure I understand what you're suggesting.

I mean we should handle the situation that disp beyonds 12-bit range in addi or prefetch.w.

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PR: https://git.openjdk.org/jdk/pull/10884