RFR: 8295948: Support for Zicbop/prefetch instructions on RISC-V [v6]

[Ludovic Henry]

On Mon, 7 Nov 2022 14:46:08 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> I'm not sure I understand what you're suggesting.
>
> I mean we should handle the situation that disp beyonds 12-bit range in addi or prefetch.w.

How about we add an assert for now? That `disp` value is driven by `AllocatePrefetchDistance`, `AllocatePrefetchStepSize`, and `AllocatePrefetchLines`/`AllocateInstancePrefetchLines`. Given the default value of these config variables, the maximum `disp` would be `3*CacheLineSize + max(3,1) * CacheLineSize` which is (on most platforms) 384 bytes. If you max-out the number of lines to prefetch, you'd get `3*CacheLineSize + 64 * CacheLineSize` or 4288 bytes which indeed requires more than 12 bit of storage.

Either we can safeguard against that in `vm_version_riscv.cpp` (given these values are quite nonsensical in themselves, given the cost/benefit of doing so many prefetches or so far). Either we can complexify the code generation here in that case.

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PR: https://git.openjdk.org/jdk/pull/10884