RFR: 8295270: RISC-V: Clean up and refactoring for assembler functions [v4]

[Fei Yang]

On Fri, 14 Oct 2022 06:14:26 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix code comments
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 480:
> 
>> 478:   void bge(Register Rs1, Register Rs2, Label &L, bool is_far = false);
>> 479:   void bltu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
>> 480:   void bgeu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
> 
> Do you want to line things like these up? For example:
> 
> 
> 
>   void beq (Register Rs1, Register Rs2, Label &L, bool is_far = false);
>   void bne (Register Rs1, Register Rs2, Label &L, bool is_far = false);
>   void blt (Register Rs1, Register Rs2, Label &L, bool is_far = false);
>   void bge (Register Rs1, Register Rs2, Label &L, bool is_far = false);
>   void bltu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
>   void bgeu(Register Rs1, Register Rs2, Label &L, bool is_far = false);

Yes, that looks better. Fixed.

-------------

PR: https://git.openjdk.org/jdk/pull/10697