RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v4]

[Yadong Wang]

On Tue, 18 Oct 2022 09:03:36 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> Similarly to AArch64 DC.ZVA, the RISC-V Zicboz [1] extension provides the cbo.zero [2] instruction that allows to zero out memory a cache-line at a time. This should be faster than storing zeroes 64bits at a time.
>> 
>> [1] https://github.com/riscv/riscv-CMOs
>> [2] https://github.com/riscv/riscv-CMOs/blob/master/cmobase/Zicboz.adoc#insns-cbo_zero
>
> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
> 
>   fixup! Add -XX:CacheLineSize= to set cache line size

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4126:

> 4124:   srai(t1, t0, 3);
> 4125:   sub(cnt, cnt, t1);
> 4126:   add(t2, zr, zr);

The usage of temporary registers needs to be made known to C2. You'd better pass arguments in and add effect in the ad file.

-------------

PR: https://git.openjdk.org/jdk/pull/10718