RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v4]

[Ludovic Henry]

On Tue, 18 Oct 2022 09:35:25 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

>> Ludovic Henry has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   fixup! Add -XX:CacheLineSize= to set cache line size
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4126:
> 
>> 4124:   srai(t1, t0, 3);
>> 4125:   sub(cnt, cnt, t1);
>> 4126:   add(t2, zr, zr);
> 
> The usage of temporary registers needs to be made known to C2. You'd better pass arguments in and add effect in the ad file.

Given it's only made to be called from `StubRoutine::zero_blocks` stub routine and `t0-t1` are temporary registers and `t2` (aka `x7`) is caller-saved, I don't understand why it needs to be made aware for C2?

I'll add them as `tmp0-tmp3` arguments to `MacroAssembler::dcache_zero_blocks` to make sure any future caller of this will be aware.

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PR: https://git.openjdk.org/jdk/pull/10718