RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v4]

[Yadong Wang]

On Tue, 18 Oct 2022 12:46:33 GMT, Ludovic Henry <luhenry at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4126:
>> 
>>> 4124:   srai(t1, t0, 3);
>>> 4125:   sub(cnt, cnt, t1);
>>> 4126:   add(t2, zr, zr);
>> 
>> The usage of temporary registers needs to be made known to C2. You'd better pass arguments in and add effect in the ad file.
>
> Given it's only made to be called from `StubRoutine::zero_blocks` stub routine and `t0-t1` are temporary registers and `t2` (aka `x7`) is caller-saved, I don't understand why it needs to be made aware for C2?
> 
> I'll add them as `tmp0-tmp3` arguments to `MacroAssembler::dcache_zero_blocks` to make sure any future caller of this will be aware.

C2 generates ClearArrayNodes, which emit zero_words -> zero_blocks directly. I don't find any caller-saving logic there. t0 is free to use (not participating in register allocation), but t1 is used as condition code in C2. base and cnt registers can be colloberred safely because they were indentified as USE_KILL.

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PR: https://git.openjdk.org/jdk/pull/10718