RFR: 8295282: Use Zicboz/cbo.zero to zero-out memory on RISC-V [v6]

[Ludovic Henry]

On Thu, 20 Oct 2022 14:16:52 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Ludovic Henry has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Explicit use of temp registers
>>  - fixup! Add -XX:CacheLineSize= to set cache line size
>
> src/hotspot/cpu/riscv/vm_version_riscv.cpp line 48:
> 
>> 46: 
>> 47:   if (!FLAG_IS_DEFAULT(CacheLineSize) && !is_power_of_2(CacheLineSize)) {
>> 48:     warning("CacheLineSize must be a power of 2");
> 
> TBH, I am worried about the case when user specified some inaccurate cache-line size here, especially when the specified value is bigger than the actual cache-line size. The currently implementation won't work in that case. We really need some way to determine the cache-line size at runtime to be safe.

That was done to answer https://github.com/openjdk/jdk/pull/10718#discussion_r996410678. Ideally it would be detected at runtime. However, I don't know of any API in RISC-V or Linux to get that information.

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PR: https://git.openjdk.org/jdk/pull/10718