Integrated: 8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

[Fei Yang]

On Fri, 2 Sep 2022 03:34:49 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Currently G1 (and Shenandoah) implicitly uses x13 in oop_store_at on riscv.
> 
> This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186).
> This would be fixed in the same way on riscv by passing the temporary register explicitly so it is part of the GC API.
> 
> Testing: Passed Tier1 test on linux-riscv64 SiFive Unmatched board.

This pull request has now been integrated.

Changeset: 5bed9f76
Author:    Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/5bed9f767507bb0f123247d149ead84d2d635f52
Stats:     71 lines in 16 files changed: 2 ins; 0 del; 69 mod

8293290: RISC-V: Explicitly pass a third temp register to MacroAssembler::store_heap_oop

Reviewed-by: shade

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PR: https://git.openjdk.org/jdk/pull/10137