RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v2]

[Fei Yang]

On Mon, 5 Sep 2022 14:58:00 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/gc/shared/barrierSetAssembler_aarch64.cpp line 288:
>> 
>>> 286: 
>>> 287:   // Is it a weak but alive CLD?
>>> 288:   __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));
>> 
>> No need to save r11 then?
>
> As `resolve_weak_handle` may call into the VM `r11` may still be clobbered. The reason that `rscratch[1/2]` was not used previously was because  some GC in the `resolve_weak_handle` call graph used them implicitly. This is all explicit now so `rscratch` is used instead as it seems like it is the way the GC API has gone, with all registers being explicit. 
> 
> There is still some room for improvement here with regards to being more consistent with what registers are used.

"As resolve_weak_handle may call into the VM r11 may still be clobbered. "
-- I don't quite understand this.  If this is the case, shouldn't r11 be saved & restored immediate before and after the VM call together with other live caller-save registers?

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PR: https://git.openjdk.org/jdk/pull/10161